1. Field of the Invention
The present invention relates to integrated circuit devices, and more particularly to devices for protection of integrated circuits from plasma damage during manufacture.
2. Description of Related Art
The subject of protecting integrated circuits from plasma damage has received much attention from circuit designers interested in protecting device gates. In the manufacturing of integrated circuits, the processes include plasma treatments. For example, backend processing, such as metal etching, photoresist stripping, and deposition of dielectrics, involves plasma which induces charge on the structures being treated. The plasma-induced charge damages underlying structures in the device, including structures critical to device performance. For example, tunnel dielectrics used in flash memory and gate dielectrics are damaged by plasma-induced charge. Furthermore, the charge storage structures utilized in SONOS, N-bit memory (charge trapping memory cell that can trap
charge at different positions of the charge trapping structure), and PHINES are particularly susceptible to damage by plasma-based processes.
The plasma-induced charge may be either positive or negative, and different types of damage can occur based on the type of plasma-induced charge.
In prior art semiconductor memory integrated circuits, each word line driver 101 is combined with its own protection circuit distinct from the word line driver 101, such as the CMOS transistor pair 102 shown in FIG. 1. The word line driver 101 provides different operation voltages to a word line 106 in the course of memory operations. The CMOS transistor pair 102, including PMOS 103 and NMOS 105, passes plasma-induced charge to the semiconductor substrate. The positive charge is passed through PMOS 103 and the negative charge is passed through NMOS 105. Each word line of the word line driver has its own protection circuit, such as a CMOS transistor pair. However, this design occupies a great deal of chip space and reduces the circuit density. This plasma protection circuit design presents an obstacle to the continued miniaturization of integrated circuit dimensions.